The present invention generally relates to a method for forming a pattern of a semiconductor device, and, more specifically, to a method for forming an ultra fine pattern using a spacer patterning technology to overcome resolution limits of an exposer used in the manufacture of semiconductor devices.
In order to improve integration of the semiconductor device, a photolithography technology has been developed. The photolithography technology can form fine patterns using Deep Ultra Violet (DUV) light sources, such as, ArF (193 nm) and VUV (157 nm), and chemically amplified photoresist materials suitable for the exposer light sources.
As a semiconductor device becomes smaller, it is important to control a critical dimension of a pattern line-width in the photolithography technology. Generally, the processing speed of semiconductor devices depends on the critical dimension of the pattern line-width. For example, when the size of the pattern line-width is decreased, the processing speed is increased to improve device performance.
However, in the photolithography process, it is difficult to form a line and space (L/S) pattern of less than 40 nm by a single exposure process using an ArF exposer having a common numerical aperture of less than 1.2.
In order to improve resolution of a photolithography technology and extend a process margin, a double exposure technology has been developed. The double exposure technology includes processes whereby a photoresist-coated wafer is exposed twice using two masks, and then developed.
Since the double exposure technology uses two masking processes for patterning, the process is complicated in comparison with the case using a single mask, and the manufacturing cost and the turn-around-time are greater than those of a single patterning technology using a single mask, thereby degrading the throughput. When a pattern having a smaller pitch than a resolution limit of the exposer is formed in the cell region, illusory images are overlapped. As a result, the double exposure technology may not result in a desired pattern. Furthermore, during alignment of the masks, overlays may be misaligned.
In order to prevent the overlapping and misalignment, i) a double patterning technology (DPT) and ii) a spacer patterning technology (SPT) have been used.
The DPT comprises forming a first pattern having a pitch twice as large as that of a desired pattern, and forming a second pattern having the same pitch, but between the first patterns. The DPT may use two different methods to form the pattern: a positive method or a negative method.
As shown in FIG. 1, in the positive method, a stacked structure including an underlying layer 12, a first hard mask film 14, a second hard mask film 16 and a first positive photoresist pattern 18a is formed over a semiconductor substrate 10. A second hard mask pattern 16a is formed using the first positive photoresist pattern 18a as an etching mask. A second positive photoresist pattern 18b is formed in between the second hard mask patterns 16a. A first hard mask pattern 14a is formed using the second hard mask pattern 16a and the second positive photoresist pattern 18b as etching masks.
As shown in FIG. 2, in the negative method, a stacked structure including an underlying layer 22, a first hard mask film 24, a second hard mask film 26 and a first negative photoresist pattern 28a is formed over a semiconductor substrate 20. A second hard mask pattern 26a is formed using the first negative photoresist pattern 28a as an etching mask. A second negative photoresist pattern 28b is formed over the second hard mask pattern 26a. The second hard mask pattern 26a is etched using the second negative photoresist pattern 28b as an etching mask. The second negative photoresist pattern 28b is removed, and the first hard mask film 24 is etched using the second hard mask pattern 26a as an etching mask to form a first hard mask pattern 24a. 
Since the DPT methods use two separate masking processes, it is possible to form a pattern having a smaller pitch size. However, the process steps are complicated, and the manufacturing cost is increased. Moreover, when the second photoresist pattern is formed, misalignment can occur.
The SPT is a self-alignment technology for preventing misalignment by using spacers for forming a pattern in a cell region. The SPT may be performed two different ways: a positive method or a negative method.
As shown in FIG. 3, in the positive method, a stacked structure including an underlying layer 32, a first hard mask film 34, a second hard mask film 36 and a photoresist pattern 38a is formed over a semiconductor substrate 30. A second hard mask pattern 36a is formed using the first photoresist pattern 38a as an etching mask. A spacer 38b is formed at sidewalls of the second hard mask pattern 36a. The second hard mask pattern 36a is removed, and a first hard mask pattern 34a is formed using the spacer 38b as an etching mask.
As shown in FIG. 4, in the negative method, a stacked structure including an underling layer 42, a first hard mask film 44, a second hard mask film 46 and a photoresist pattern 48a is formed over a semiconductor substrate 40. A second hard mask pattern 46a is formed using the photoresist pattern 48a as an etching mask. A spacer 48b is formed at sidewalls of the second hard mask pattern 46a. A spin-on-glass film 50 is coated over the resulting structure. A CMP or an etch-back method is performed to expose the second hard mask pattern 46a. The spacer 48b is removed, and a first hard mask pattern 44a is formed using the second hard mask pattern 46a and the spin-on-glass film 50 as etching masks.
FIG. 5 is a cross-sectional diagram illustrating a conventional SPT method. A stacked structure including an underlying layer 32, a first hard mask film 34 and a second hard mask pattern 36a (e.g., amorphous carbon) is formed over a semiconductor substrate 30.
A chemical vapor deposition (CVD) method is performed on the first hard mask film 34 including the second hard mask pattern 36a, creating a nitride film 38. The nitride film 38 is etched by an etch-back process, thereby obtaining a spacer 38b at sidewalls of the second hard mask pattern 36a. 
The second hard mask pattern 36a is removed. A polysilicon film included in the top layer of the first mask films 34 is etched using the spacer 38b as an etching mask, thereby forming a first hard mask pattern 34a. The spacer 38b is removed.
As mentioned above, since a nitride film is formed by a CVD method and a multi-layered mask film is applied in order to form a spacer in the conventional SPT method, the etching process is repeated several times. As a result, the process is complicated, the manufacturing cost is high, and the process time is long. Moreover, the operation of CVD equipment is complicated. Furthermore, after an etch-back process, a horn shape can be formed on the spacer (i.e., impurities that have attached to the spacer). As the critical dimension of the spacer becomes smaller, the pattern profile can be degraded by this horn shape.